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radR project > Features and Plugins > Ettus Research USRP-1 + gnuradio software as a radar digitizing system
Ettus Research USRP-1 + gnuradio software as a radar digitizing systemFrom $1Table of contents
The GNUradio project is an open-source "software-defined radio" project. The codebase supports various hardware, including the "USRP" (Universial Software Radio Peripheral) series of high-speed devices produced by Ettus Research. Although not intended for this purpose, the USRP-1 and the LFRX (Low-Frequency Receiver) daughterboard can be adapted (with minor hardware and significant firmware/software changes) to act as a high-quality marine (pulsed, scanning) radar digitizing card attaching to a host PC via USB (or ethernet, for other USRP models). This page describes how we did it. Source code, FPGA (field-programmable gate array) build, and schematics are attached to the page. This digitzing card works with radR under both Linux and Windows, using the usrp plugin. Here are two views of the prototype: 6 May, 2011: These photos show the version 2.0 interface scheme, in which ARP (heading) and ACP (azimuth) connections have been moved from a 2nd LFRX daughterboard to auxilliary digital inputs on the first LFRX daughterboard. This saves power, reduces cost, and allow this basic scheme to be used in the 14-bit family of USRPs, which can only host a single receiver daughterboard. 13 May 2011: The plugin has now been built under windows. This screenshot shows indoor testing with a synthetic pulse source triggered by the Furuno (whose own magnetron is disabled): The customized USRP-1Our FPGA build and host-side code has the following features: USB packetsThere are 256 16-bit words in each USB packet. The upper 4 bits (or eventually upper 2 bits, for the 14-bit USRP model) are used to hold up to 1024 (or up to 512 for the 14-bit USRP model) bits of metadata - see below. Digitizing modesOne of these is active at a time. The mode is selected by sending a command to the USRP.
Metadata Every USB packet is stamped with a serial number (32 bits) encoded in the first 32 available bits of metadata (i.e. top 4 bits of bytes 0, 2, 4, ..., 14 for the 12-bit unit; top 2 bits of bytes 0, 2, 4, ..., 30 of 14-bit unit). // NB: order of fields in metadata must be reverse of instance "stage_4" of pack_metadata in usrp_bbprx.v unsigned int USB_serial_no; // serial number of USB packet unsigned int n_ACPs; // number of ACPs since last reset unsigned int n_ARPs; // number of ARPs since last reset unsigned int n_trigs; // number of triggers since last reset unsigned int ACP_interval_last_ARP; // ticks in ACP interval that included last ARP pulse (only valid once n_ACPs != ACP_count_last_ARP) unsigned int ACP_age_last_ARP; // ticks since last ACP pulse at last ARP pulse unsigned int ACP_count_last_ARP; // ACP counter at last ARP pulse unsigned int ticks_since_last_ACP; // clock ticks since last ACP pulse unsigned int ticks_since_last_ARP; // clock ticks since last ARP pulse unsigned int ACP_interval; // clock ticks between most recent consecutive ACP pulses that contained a trigger pulse unsigned int ARP_interval; // clock ticks between most recent consecutive ARP pulses unsigned int trig_interval; // clock ticks between most recent consecutive trigger pulses unsigned long long clock_ticks; // number of (64MHz) clock ticks since last reset Note:
Sampling rateThe following diagram illustrates the buffers data pass through along the way from the ADC to the USB bus. It also shows sustained rates possible for transfer between buffers, in both megabytes per second (MB / s) and 512-byte packets per second (P/s): USB bus <------- Cypress FX/2 TX buffer (2 KB) <------ FPGA TX FIFO (8 KB) <-------- ADC 32 MB/s 96 MB/s 128 MB/s = 64 MSPS * 2 Bytes / sample 64 KP/s 192 KP/s 256 KP/s Over the long run, because we only transmit data when a trigger pulse is detected, and only for a preset listening interval, we can sustain digitizing 4096 samples per pulse at PRF=2100, because this is a total data rate of 4096 * 2100 * 2= 17.2 MB/s, well within the USB bus bandwidth. Moreover, because the 8KB FPGA TX FIFO can be filled at full speed, we are guaranteed to be able to capture 4096 consecutive samples at 64 MSPS before filling it. The rest of the pipeline then empties the FIFO at a lower rate, but in sufficient time before the next incoming trigger pulse. Theoretically, we should be able to digitize pulses at 4 K samples per pulse up to a PRF of about 32 MB / s / (8 KB / pulse) = 4 K pulse / s; i.e. a PRF of 4096 Hz. And if we are willing to reduce the number of samples per pulse to 2K, then we should be capable of digitizing up to PRF = 8192 Hz. In tests, the radR software has been able to sustain incoming data gated to 4096 pulses per sweep at 25 RPM, 4096 samples per pulse, and 64 MSPS, for a total bandwidth of 14.0 MB/s entering radR (with 17.2 MB/s entering the USRP host-side code from the USB bus) - see the sample blipmovie attached below. Proposal for Hardware front-end using LFRX card (May 2012: Note; upcoming changes to the USRP front-end do not necessarily follow this scheme.)To allow control of and acquisition of data from serial devices in a time-pinned way (so that we know which radar data correspond to what states of the devices), and to reduce the number of ADC channels required for the radar from 4 (current build) to 2 (next version), here is a proposal for interfacing the USRP to the standard quad of radar signal lines via a single LFRX card. Exising (version 2.0) approach:
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